The present invention concerns input/output busses for computing systems and pertains particularly to logic implementation of control signals for an on-silicon multi-master data transfer bus.
For an input/output (I/O) bus, such as an I/O bus which uses the Peripheral Component Interconnect (PCI) bus protocol, a pull-up resistor is required for certain signals in order to maintain an inactive state. For example, in the PCI bus protocol, the following sustained tri-state and open drain signals require a pull-up resistor to maintain an inactive state: FRAME#, IRDY# TRDY#, STOP#, LOCK#, DEVSEL#, PERR#, SERR#, INTA#, INTB#, INTC#, INTD#, CLKRUN#, REQ64#, and ACK64#. These tri-state and open drain signals often are required to maintain an inactive state for many clock signals.
While use of tri-state and open drain signals which require a pull-up resistor is generally an efficient way to implement an I/O bus, this is not an efficient strategy when using the bus protocol to connect logic blocks within a single integrated circuit. This is because pull-up resistors which are capable of meeting the specifications for buses that operate in accordance with the PCI bus are generally not available on an integrated circuit. Thus, on an integrated circuit, "bus keepers" whose purpose is to keep tri-stated signal voltage levels from drifting out of specification for inordinate lengths of time are not guaranteed to keep a tri-stated signal in its inactive state and may switch to an active state unintentionally.
When integrating functional blocks connected by a PCI bus onto a single integrated circuit, it is therefore generally necessary to strip off the PCI local bus interface from the blocks to be integrated and to define new bus protocol control signals which are not shared. However, this stripping of the PCI protocol bus interface creates many problems to design integrity. Further, defining and verifying a new bus protocol control requires resources and time. Additionally, a new bus protocol, while optimal for one project may be less optimal for another project. Also, stripping off a PCI protocol bus interface and substituting another bus interface greatly increases the risk of introducing logic and architectural errors because of the dramatic changes to blocks that have been verified already as functionally and architecturally correct with the PCI local bus interface.